1. Field of the Invention
The present invention relates generally to semiconductor memory devices, and, more particularly, to a wafer burn-in test circuit for sensing a defective memory cell of a semiconductor memory device.
2. Description of Related Art
Generally, a burn-in test for ensuring the reliability of a semiconductor memory chip is performed after wafer fabrication is completed, and more specifically, after the chip has already been assembled and packaged. Chips which are found to be defective are discarded. Since the defective chips are screened out after the assembly and packaging processes have been completed, a significant amount of time and money is wasted.
In dynamic random access memories (DRAMs), the time required to test for defects is inordinately long, as most defects are single bit defects, usually associated with leakage current of an imperfect memory cell. The leakage current is usually caused by defects in the transfer gate oxide layer, capacitor dielectric layer, storage node junction, or the like.
In a conventional burn-in test, the efficiency at which a stress voltage is supplied to a memory cell is very low due to the fact that only one word line is selected per few thousand cycles (e.g., every 4,096 or 8,192 cycles in the case of a 64 Mb DRAM). Of course, this problem is exacerbated by the ever-increasing packing densities of semiconductor memory devices. In this regard, in order to reduce burn-in time and raise the efficiency at which the stress voltage is supplied, a burn-in technique in which all the word lines are simultaneously selected has been adopted. Such a technique is disclosed in detail in an article entitled "Wafer Burn-in (WBI) Technology for DRAMs", IEDM, 1993, pp. 639-642.
With reference now to FIG. 1, a conventional burn-in test circuit will now be described. More particularly, a typical memory cell array includes word lines WLO-WLn connected to a word line driver 6 and to the gate electrode of respective transfer transistors 2, and complementary bit lines BL and/BL connected to a sense amplifier 8. Data stored in storage capacitors 4 are transferred to the bit lines BL and /BL through respective ones of the transfer transistors 2. Each associated transfer transistor 2 and storage capacitor 4 pair constitutes a memory cell.
The conventional burn-in test circuit includes a plurality of transistors 10 connected between respective ones of the word lines WLO-WLn and a gate electrode voltage (Vg) line. The transistors 10 each have a small-sized channel. In operation, a burn-in test is performed by simultaneously applying a stress voltage Vstress to the gate electrodes of all of the transistors 10, and then simultaneously applying a gate electrode voltage Vg to the gate electrodes of the transfer transistors 2, via the small-sized channels of the transistors 10. A stress voltage of a desired level can be supplied to the dielectric layer and storage node junction of the capacitors 4 by appropriately controlling a plate voltage VPL applied to the storage plate electrode of the capacitors 4, and a voltage applied to the bit lines BL and/BL, from the exterior of the chip. In this manner, a wafer burn-in test circuit supplies a high stress voltage to the gate electrode of the transfer transistors 2 so that even a small leakage current (evidencing a defective memory cell) can be sensed.
With reference now to FIG. 2, a word line structure of a low integration density DRAM (e.g., a 16 Mb DRAM) has a sufficient word line pitch to enable a metal strap having a low resistance to be strapped to a gate polysilicon having a higher resistance, to thereby enhance the on/off characteristics of the word lines. With this word line structure, the wafer burn-in test circuit depicted in FIG. 1 can perform satisfactorily.
With reference now to FIG. 3, a word line structure of a high integration density DRAM (e.g., a 64 Mb DRAM) has a much narrower word line pitch and much smaller memory cells, thereby rendering it exceedingly difficult to strap metal to all of the polysilicon word lines, thus necessitating a split word line driver (SWD) structure. Since the split word line driver requires only one metal line per 4-8 word lines, it is excellent from the standpoint of providing a sufficient metal pitch. However, due to the split word line structure, it is difficult to supply a stress voltage to the memory cells via transistors having a small channel size, such as in the conventional wafer burn-in test circuit depicted in FIG. 1.
Based on the above, it can be appreciated that there presently exists a need in the art for a burn-in test circuit for a semiconductor memory device which overcomes the drawbacks and shortcomings of the presently available technology. The present invention fulfills this need.